New design reduces the areal footprint of nanowire transistors by a factor of two

3D silicon is all the rage, and now nanowire transistors have further potential to keep Moore's Law on life support. Researchers at A*STAR have found a way to double the the number of transistors on a chip by placing the atomic-scale wires vertically, rather than in the run-of-the-mill planar mode, creating two "wrap-around gates" that put a pair of transistors on a single nanowire. In the future, tech could be merged with tunnel field effect transistors -- which use dissimilar semiconductor materials -- to create a markedly denser design. That combo would also burn a miniscule percentage of the power required conventionally, according to the scientists, making it useful for low-powered processors, logic boards and non-volatile memory, for starters. So, a certain Intel founder might keep being right after all, at least for a few years more.Researchers take nanowire transistors vertical, double up on density originally appeared on Engadget on Thu, 21 Jun 2012 08:49:00 EDT. Please see our terms for use of fe

New design reduces the areal footprint of nanowire transistors by a factor of two

Semiconductor chip makers first began the production of three-dimensional (3D) transistors in 2011. Engineers can pack more 3D transistors onto a single chip because they are much more compact ...

Wed 20 Jun 12 from Phys.org

Researchers take nanowire transistors vertical, double up on density

3D silicon is all the rage, and now nanowire transistors have further potential to keep Moore's Law on life support. Researchers at A*STAR have found a way to double the the number of transistors ...

Thu 21 Jun 12 from Engadget

Microelectronics: Two at a time

A new design reduces the areal footprint of nanowire transistors by a factor of two. Scientists have now integrated two transistors onto a single vertical silicon nanowire, pushing the areal ...

Thu 21 Jun 12 from ScienceDaily

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